1. Field of the Invention
The present invention relates to a semiconductor device, more specifically, a semiconductor device having a vertical MOS transistor.
2. Description of the Related Art
Recently, a three-dimensional structure type MOSFET in which a gate structure is made three-dimensional is proposed for increasing an integration degree of a semiconductor device. Such as the three-dimensional structure type MOSFETs, an FinFET in which a channel layer of a Fin structure is sandwiched by gate electrodes, an surrounding gate transistor (hereinafter, called SGT) in which agate electrode is formed around a silicon pillar are known.
Of them, an SGT has the structure in which the source, the gate and the drain are disposed in the perpendicular direction to the substrate, and the gate surrounds the silicon pillar. Accordingly, an SGT has the occupation area reduced significantly as compared with a planar type MOSFET. Therefore, an SGT is significantly expected to be applied to a DRAM, Flash EEP ROM and CMOS.
In an SGT structure, for example, as shown in FIGS. 11A and 11B, in Japanese Patent Laid-Open No. 6-53513, microscopic columnar protrusion (silicon pillar) 103 in a circular cylindrical shape is placed in the region surrounded by element isolation insulating film 102 formed by a LOCOS method on p-type silicon substrate 101, and a source and drain region constituted of n-type diffusion layers (upper diffusion layer 107 and lower diffusion layer 104) are respectively formed on the top portion and bottom portion of the columnar protrusion, and gate electrode 106 is formed around the columnar protrusion via gate insulating film 105. In this document, contact 109 to the gate electrode is taken from the gate material which is led outside the element isolation region. Contacts 108, 110 are connected to upper diffusion layer 107, and lower diffusion layer 104, respectively. Here, FIG. 11A is a plane view, and FIG. 11B is a sectional view.
While miniaturization of elements is underway, element isolation by a LOCOS method has the problem of being incapable of forming a microscopic element isolation region. Thus, element isolation region of 250 nm or less becomes possible by a shallow trench isolation (hereinafter, called STI).
When an SGT structure is provided by forming a silicon pillar in the region of the silicon substrate subjected to element isolation by such STI, if STI is to be formed after the silicon pillar is formed, the substrate thickness is required by that amount, and the silicon pillar has to be protected at the time of formation of STI. Thus, formation of the silicon pillar by etching the substrate after formation of STI is generally conceivable.
Thereafter, the lower diffusion layer is formed, an insulating film is formed on the silicon substrate including the side surface of the silicon pillar, the gate electrode material is deposited, and the SGT structure in which the gate electrode is formed on the side surface of the silicon pillar by etch back or the like is completed.
In the conventional planar type MOS transistor, an unnecessary portion of the gate electrode material is all removed at the time of processing the gate electrode, and therefore, the portion which becomes floating state is not formed.
However, in the case of forming the vertical MOS transistor in which the silicon pillar is formed by etching the silicon substrate at the area surrounded by the STI region, the channel part is formed by covering the silicon pillar with the gate insulating film and the gate electrode, and the diffusion layers to be the source and drain are included on the top and bottom of the channel part, the gate electrode material remains on the side surface of the STI insulating film at the time of formation of the gate electrode.
The gate electrode material remaining on the side surface of the STI insulating film is brought into a floating state, and as a result, when electric charge is injected into the gate electrode material brought into the floating state by certain influence during operation of the MOS transistor, its potential changes to cause the problem that the parasitic MOS in the STI region operates.
When the diameter of the silicon pillar is made smaller, the contact to the upper diffusion layer and the contact to the gate electrode move closer to each other, and ultimately, separation of the contacts becomes difficult. As shown in Japanese Patent Laid-Open No. 6-53513, leading the gate contact to the outside of the element isolation region is difficult due to interference of the height of the STI insulating film, and formation of the gate contact with an easier method is desired.
The present inventor has recognized that, in the vertical MOS transistor in which the silicon pillar is formed by etching the silicon substrate at the portion surrounded by the STI region, the channel part is formed by covering the silicon pillar with the gate insulating film and the gate electrode, and the diffusion layers to be the source and drain are included on the top and bottom of the channel part, the parasitic MOS operation by the gate electrode material remaining on the side surface of the STI insulating film becomes a problem.
Further, separation of the upper diffusion layer contact and the gate contact when a microscopic silicon pillar is formed is difficult.